1. Field of the Invention
The present invention relates to integrated circuits that include a field programmable gate array.
2. Description of the Prior Art
Integrated circuits (ICs) have traditionally implemented a single function, or else functions that were defined by software programming. However, in either case, the logic architecture that implemented the functionality was fixed during the design of the IC. More recently, integrated circuits have been developed whose logic architecture can be changed after manufacture. For example, Field Programmable Gate Arrays (FPGAs) have been developed whose logic functions can be established by the user. Referring to FIG. 1, a typical FPGA architecture is illustrated. The logic functions are typically done in Programmable Function Units (PFUs) 100, 101, 102, 103, which are alternatively referred to by workers in the art as Configurable Logic Blocks (CLBs). Each PFU includes various logic circuit elements (AND gates, OR gates, NAND gates, NOR gates, flip-flops, multiplexers, registers, latches, and tri-state buffers, for example) that may be connected in a desired arrangement in order to implement desired logic and memory functions. For example, typical logic functions include combinatorial logic, adders, counters, and other data path functions. The combinatorial logic may be performed using look-up tables (LUTs) or logic gates, whereas sequential logic is typically performed using storage elements (registers) such as flip-flops and latches.
As illustrated in FIG. 1, the PFUs are connected together by Routing Nodes (R-nodes), being illustratively the conductors in groups 104, 105, 106 and 107. In addition, Configurable Interconnect Points (CIPs) are used to connect two or more R-nodes together. The CIPs may be grouped as C-blocks (e.g., 108) and S-blocks (e.g., 109), whose functions are described below. (In a more recent type of FPGA design, a third set of conductors, referred to as "switching R-nodes" are used to make connections. These implement the functionality of the C-blocks and S-blocks in a manner that provides additional routing flexibility with a reduced total number of CIPs. However, more CIPs per path are typically required. Hence, the problems addressed herein are common to both types of designs). Due to their symmetric layout, FPGAs may conceptually be divided into more or less identical blocks of circuitry called Programmable Logic Cells (PLCs). For example, a given PLC (117) typically includes a single PFU (101), and the associated R-nodes and CIPs as described above. Around the periphery of the integrated circuit are programmable Input/Output cells (e.g., 111, 112), also referred to as "PIC" herein. These include Input/Output blocks (e.g., 113, 114, 115 and 116) that communicate externally to the integrated circuit via bondpads (e.g., 117, 118, 119, 120).
FIG. 2 then shows an example of how the connections inside the C-Block and S-Block can be implemented. In FIG. 2(A), a C-block is illustrated, wherein the vertical routing conductors 201 and 202 may be selectively connected to the horizontal routing conductor 203 by means of the CIPs 205 and 206. Similarly, the vertical routing conductors may be connected to the other horizontal conductors 204, 207, 208, 209 and 210 by the other CIPs illustrated. As shown in FIG. 2(A), each CIP is illustrated as a diamond, and typically comprises a field effect transistor having a first source/drain region connected to the vertical conductor, and a second source/drain region connected to the horizontal conductor. In FIG. 2(B), a typical S-block 250 is illustrated. The vertical conductor 251 is selectively connected to the horizontal conductor 253 by means of transistor 257, and to the horizontal conductor 254 by means of transistor 258. Similarly, the vertical conductor 263 is selectively connected to horizontal conductors 253 and 254 by means of transistors 259 and 260, respectively. The vertical conductors 251 and 263 are selectively connected together by transistor 262, whereas the horizontal conductors 253 and 254 are selectively connected together by transistor 261. In an analogous manner, the vertical conductors 252 and 264 and the horizontal conductors 255 and 256 may be selectively connected by the other transistors shown.
In the above embodiment, the gate of a given transistor is controlled by a register (not shown), or other means of storing the desired connectivity information. In the case of an n-channel transistor, when the gate voltage on the transistor is high, the transistor conducts, which connects the two conductors. When the gate voltage is low, the transistor does not conduct. The gate voltage is typically controlled by a program register or electronically-erasable programmable read-only memories (EEPROMs). However, in lieu of field effect transistors, these connections may alternatively be made by other means, including electrically blown fuses and anti-fuses, for example. However, a drawback to these configurable connections is that a signal takes a longer amount of time to propagate through them, as compared to connections made through continuous conductors only (i.e., without a CIP). For most sections of the circuit implemented by the FPGA, the extra delay for the configurable routing can be tolerated for internally-generated signals. However, an application's input/output (I/O) signals are the signals which connect to an I/O pad, typically through either an input or output driver, and tend to be more demanding. These signals are often clocked when going out of the integrated circuit chip, and latched when coming in; they typically must be very fast. This is especially true for the I/O signals that connect directly from an I/O pad to the input or output of a register.
This problem has been addressed in some previous FPGA architectures by placing dedicated registers near the input/output (I/O) pads in the PICs. As shown in FIG. 3, a typical PLC 300 is shown that includes a PFU 302, which supplies an output signal to the PLC routing resources 307, which then programmably supply it to the PIC 301. The "data" output signal is clocked via a special register, being flip-flop 303, and supplied to the I/O bondpad 306 via the output driver 305. The 4-to-1 multiplexer 304 allows for selection of the non-inverted Q output of flip-flop 303, or the inverted output via inverter 307. It also allows for the "data" signal, or inverted "data" signal via inverter 308, to bypass the flip-flop 303 so as to be supplied in unclocked form externally to the integrated circuit. As noted above, the placement of the flip-flop 303 near the output bondpad allows for high-speed clocking of the signal off the integrated circuit chip. Note however that the output signal must travel from the PFU to the PIC via the routing resources 303, which includes R-nodes and at least one CIP, as described above. A similar situation exists with regard to the input circuitry, as shown in FIG. 4. The PIC includes the I/O bondpad 401, which in practice may be physically the same as I/O bondpad 306 in the output circuit. The input signal is supplied via input buffer 402 to the special register 403, and then via the routing resources 404 to the PFU 405 in the PLC 406. Again, the routing resources 404 include R-nodes and at least one CIP. In both cases, the special registers can be accessed only by the I/O pads, and have different functionality from those in the internal FPGA.
As shown in both FIGS. 3 and 4, the registers (303,403) in the PICs tend to have fewer inputs (such as clock enables and local set/resets) than those in the PFUs. For example, the PFU 302 includes a register, being illustratively flip-flop 309, that can receive a signal from the look-up table 310, which allows for accomplishing combinatorial logic. The look-up table may be bypassed by the multiplexer 311 if desired, and either a local or global reset may be supplied via OR gate 312. The PFU output is supplied to the routing resources via output driver 313. It can be seen that the PFU 405 in FIG. 4 is identical with that shown for FIG. 3. (It will be appreciated by workers in the art that numerous other PFU designs are possible.) Also as shown, there is typically a direct connection from a LUT to each of the registers in each PFU. However, the LUT is not available for the registers in the PICs. Hence, this prior-art solution is undesirable for many reasons, especially because the special registers in the PICs waste area on the integrated circuit if the I/O signals do not need to be latched. Furthermore, the presence of the special registers makes the software needed to configure the FPGA more difficult to implement. This is because the software must handle two distinct types of registers, as well as the fact that some registers have fast connections to an associated LUT, whereas others do not. Therefore, it would be desirable to have a circuit design that does not exhibit these problems.